Keyboard checking alarm



Aug. 23, 1955 w. s. OLlWA KEYBOARD CHECKING ALARM 2 Sheets-Sheet 1 Filed Nov. 8, 1952 NVENTOR WALTER s. OLIWA ATTORNEY 8" 3, 1955 w. s. OLIWA KEYBOARD CHECKING ALARM 2 Sheets-Sheet 2 Filed Nov, 8, 1952 L m N .m m m vm m w fi A moEEzuo 5552 V XII m\ am M33". on I E5500 525 ATTO R N EY United States Patent Office 2,716,230 Patented Aug. 23, 1955 KEYBOARD CHECKING ALARM Walter S. Oliwa, Summit, N. 5., assigncr to Monroe Calculating Machine Company, Grange, N. J., a corporation of Delaware Application November 8, 1952, Serial N 0. 319,555

6 Claims. (Cl. 340-345) This invention relates to electronic computers and more particularly to a keyboard checking circuit for use therein.

Where information is entered into an electronic computer or the like through the medium of a manually operable keyboard, it is desirable to warn the operator of the latter when a contact failure or other circuit malfunction prevents his manipulations from being transformed into the desired electrical phenomena.

The principal object of the invention, therefore, is the provision of means to the above end.

In the preferred embodiment the invention is applied to a keyboard wherein each key effects operation of selected ones of a plurality of code forming means and actuation of normally disabled timing means for conditioning the code forming means for timely operation. According to the invention a control device is set to one state on operation of each key and is reset to the opposite state on successful actuation and operation of the timing means. A coincidence detector, controlled jointly by the control device and an electronic element that is caused to assume a desired state of conduction while each key is operated, actuates an alarm whenever the control device is in the set state and the electronic element is in its normal state of conduction.

Other objects and features of the invention will become apparent from the following description when read in the light of the drawings of which:

Figs. 1 and 2, taken together, constitute a schematic wiring diagram of the means of the invention;

Fig. 3 is a detail wiring diagram of a coincidence gate utilized in the means of the invention;

Fig. 4 is a detail wiring diagram of an inverter utilized in the circuit of the invention; and,

Fig. 5 is a detail wiring diagram of an or gate utilized in the means of the invention.

Before entering into a description of the means of the invention, it is deemed desirable first to describe some of the components utilized repeatedly therein and shown in symbolic form in the drawings.

Referring to Fig. 3, there is illustrated a coincidence gate which in the other figures of the drawing is indicated by an encircled G and which comprises a pentode 1 having its cathode grounded and its anode connected to the juncture of the two positivemost sections of a threesection voltage divider 2. Voltage divider2is connectedbetween sources of and 100 volts and has an output line 3 extended from a center tap thereof. Control signals of substantially and -20 volts are applied to the control grid of the tube and also to the suppressor grid thereof. The tube conducts only when 0 volt signals are applied to both said grids simultaneously. Utilizing the resistor values indicated in the drawing output line 3 of the voltage divider assumes potentials of substantially 0 and -20 volts when tube 1 is cut off and conducting respectively.

Referring to Fig. 4, there is illustrated an inverter which in the other figures of the drawing is indicated by an encircled I and which includes a triode 11 having its cathode grounded and its anode connected to a voltage divider identical with the voltage divider 2 described above. Signals of 0 and -20 volts potential are applied to the grid of the triode to effect conduction and cutofi thereof respectively and output line 6 of the voltage divider assumes the opposite one of said two potentials to that which is applied to the grid.

Referring now to Fig. 5, there is illustrated an or gate which in the other figures of the drawing is indicated by an encircled V and which includes a pair of triodes 7 having their anodes commonly connected to a source of +100 volts potential and their cathodes commonly connected through a resistor 8 to a source of -20 volts potential. An output line 9 is extended from the cathodes of the two triodes. Signals of 0 and -20 volts are applied to the grid of each tube to effect conduction and cutoff thereof respectively. When both tubes are cut off, output line 9 is maintained at a potential of substantially -20 volts. However, when either tube conducts, or both tubes, the potential level of output line 9 is raised to approximately 0 volts.

Hereafter, it will be convenient to refer to the 0 and -20 volt potential levels as high and low, respectively.

Referring to Figs. 1 and 2, the keyboard includes a series of digit keys, each comprising a switch blade 10 normally engaged with the rear contact 10A but movable to engage a front contact 12. The rear contacts 10A and the blades 10 of the several switches form a series path between ground and a source of negative potential, say l00 volts. A large resistor 13, which may have the value shown, terminates the series path at the negative source. The front contact of each switch is connected through one or more diodes 14 to a line or lines 15 indicative in binary coded decimal notation of the digit 7 represented by the switch. Each line 15 is connected to the grid of one tube of a flip-flop 16 which, as shown, may comprise two inverters of the sort described above, each having the output line of its voltage divider connected to the grid of the other. For convenience, the connection of the lines 15 to the flip-flops will be considered as means for setting the flip-flops. In order to reset the flip-flops, each is provided with a puller 17 which may be identical with the inverter described above, except that it utilizes the voltage divider of one tube of the flip-flop. The grids of the several pullers 17 are connected through a condnctor 18 with the resistor 13 described above.

Normally, that is, when none of the switch blades 10 are operated, line 18 is maintained at substantially ground potential and the pullers 17 conduct. Conduction of each puller, acting through the voltage divider of the flip-flop tube with which it is associated, maintains the flip-flop in reset condition. When a flip-flop is in this condition, the line 15 connected thereto is maintained at a low potential of -20 volts. However, when one of the switch blades 10 is operated, a high potential of 0 volt is applied to the associated line or lines 15 and through the latter to the grid of the appropriate tube of the flip-flop. Meanwhile, the pullers 17 are cut off and the rise in potential of a line 15 sets the flip-flop, which thereafter maintains the line at the potential of 0 volt. When an operated switch blade 10 is returned to normal position, the pullers 17 again become efiective and the flip-flops are reset. The purpose of the flip-flops 16 and the circuitry associated therewith is to eliminate the possibility of erroneous keyboard entries due to chatter or bounce of the switch blades 10. Said means are more fully described in the copending application of W. H. Burkhart, Serial No. 274,475.

The lines 15, besides being connected to the flip-flops 16 which maintain them at the desired potential levels, are each connected (Figs. 1 and 2) to an inverter 20 and to a coincidence gate 21. The coincidence gates 21 are also controlled by timing signals which condition the several gates for --conduc-tion, successively, as will be more fully described hereinafter. The purpose of the inverters is to efiect production of the timing signals which control the gates 21, and the outputs thereof are commonly connected through -a differentiating circuit 22 to an inverter 23. When, on operation of any switch blade 10, the associated inverter 20 is made conducting and its output drops to'a low potential, difierentiator 22 delivers a single, sharp, negatively directed pulse to {inverter 23 which is momentarily cut off thereby. The output of inverter 23 is applied to a puller 24 which may be identical with that described above and shown in Fig. 1, and which etiects setting of a flip-flop 25 An output of flip-flop 25 which is low when the same is in the""set-state-is-appliedto an or gate 26 whose output is in'turn applied-to an inverter 27. Inverter 27 is utilized to prepare a counter 28 for a cycle of operation by advancing the same to capacity in one-step-from a predetermined count at which it had previously been stopped in a manner to be described hereinafter. In order that this jumping of the counter to capacity may take place only at such times as it is possible for the computer to begin a cycle of operations, 'in short, to synchronize the counter with the computer, a synchronizing signal from the computer is applied to gate 26 along with the output of flip-flop 25. Evidently, counter 28 is jumped to capacity only when both the output of the flip-flop and the synchronizing signal assume low potentials simultaneously to cause gate 26 to apply a low potential to inverter 27. Means for producing the synchronizing signal and the other circuitry associated with the flip-flop 25 are fully described in the copending application to W. H. Burkhart et al., Serial No. 270,876 wherein the gate 26 is designated 67.

Each cycle of the computer with which the means of the invention are herein shown associated comprises l80tirneperiods. *In .orderto produce signals indicative of the several timesperiods, and by which the latter may be identifierLthe counter 28 is caused to advance through 180 steps per computer cycle. The means to this end include a pulse generator 3-0 which transmits negative pulses 'to 'the'binary counter through anor gate 29 to advance the latter, and a diode matrix .31 to which the several stages of the counter are connected and which a series of output lines that are normally maintained at a low potential of .j20 volts, but which assume high potentials of 0 volt successively to indicate the count which the counter :has attained. Matrix 3lrmay be provided with one output linefor each count o'f'the counter, butpreferably, it is provided only with output lines indicative of those counts which are pertinent to the operation of the computer.

Evidently, counter 28 in ,order to count through 180 steps must have ,a capacity of 256, that is 2 In order to halt the counter when it attains the 180th count, that output line of .matrix 31 which assumes a high potential onattainment of the 180th count (line trig) is applied to of gate 29. to block application of the negative pulses frorngenerator to the binary counter.

"Therefore, whenever a switch blade 10 is operated, inverter '27 efiects jumping of counter 28 to capacity thereby "lowering the potential on the output line of matrix 21 appropriate 'to the 180th count and allowing the negative pulses from generator 30 to control gate 29 and advance the counter through a cycle of operation.

'Inorder to reset flip-flop 25 in time to prevent a second cycle of operation of counter'28 in response to a single key operation, the flip-flop is provided with a reset puller 32 that is made conducting by a timing signal .from matrix 31 during time period 1140.

The gates 21 (Fig. .1) are conditioned for conduction successivelyduring time periods t4, t5, rte, ,and t? by the appropriate signals from matrix 31. Therefore, whena Switchblade 10 .is-.,operated. and a high potential is applied til to a selected one or ones of the gates 21, the latter become conducting during the appropriate time periods.

In order to convert the outputs of the gates 21 into serial pulses for use in the computer, the anodes of the gates are connected to a common voltage divider whose output line assumes a low potential whenever one of the gates conducts. This line is in turn applied to an inverter 33 which converts said low potentials to high potentials.

In order to warn an operator of the switch blades 10 whenever an operation of the latter fails vto result .in the production of a cyclic set of timing signals due to a circuit malfunction, and, therefore, fails to .elfect appropriate operation of the gates 21 to enter a digit representation into the computer, an alarm indicator 35 which may comprise a neon lamp is provided. Preferably, one terminal of the lamp is connected to a source of negative potential while the other is connected to the output of an inverter 36 which efiects illumination of the lamp each time the same -is cut'ofi. Inverter 36 is controlled-'bya coincidence gate 37,-to which-theoutput of a flip-flop 38 which is high when the latter is set, is applied. Also connected to gate 37 is a conductor 40 which assumes a high potential whennone of the switch blades 10 are operated and a low potential when -one of the same is operated. Evidently, gate 37 conducts and applies a -low potential to inverter 36 to actuate alarm 35 only when flip-flop 38 is in the set state and all of the switch blades 10 are in their-normal positions.

The means for setting -flip=fiop 38 comprises aninverter 41 havingits input-connected to the resistor 13 described above and its output applied to a second inverter 42.,

When all of the switch blades 10 are in their normal positions, inverter 41 conducts and inverter 42 is cut off. However, when a switch blade 10 is operated, inverter 41 is cut oil? and inverter 42 conducts. The outputof-inverter 42 is applied to 'the conductor '40 and also to a differentiating circuit 43 which, on conduction of the inverter, delivers a single, sharp, negatively directed pulse to an inverter 44 which is momentarily cut off thereby. Inverter 44 controls a puller 45 which conducts on cutoff of the-former and sets the flip-flop -38.

Flip flop 38 is reset by 'a puller '46 having the output line of matrix 31, which is high during time period to, applied thereto.

In operation, the described means serves toset-flip-flop 38 each time a switch blade 10 is operated and thereby to apply a high potential to one input of gate 37. At the same time, however, a low potential is applied to the other input of the gate over conductor 40 and the same does not become conducting. When the operated switch blade '10 is restored to normal position, a high potential is applied over conductor 40 to gate "37 but its effect on the gate is dependent on whether or not flipflop .38 has been reset. "If the flip-flop was reset by a timing signal indicative of time period to, alow potential is applied to the gate by the flip-flop and ,the gate does not conduct. However, if .a cycle of-operation.of..counter 38 .was ,not initiated, .due ,to .a contact failure or .other circuit malfunction, and, therefore, no timing signals were produced, the flip-flop 38'remained in .the set state and gate 37 conducts to efiect actuationof alarm 35. If desired, manually operable [means may the provided for resetting zflip=flop 38.

It is to be mentioned that, if desired, the flip-flop 38 may be replaced by a relay or other device having two stable states and the associated circuitry modified accordingly.

While there has been above described but a single embodiment of :the invention, it is to be understood "that many changes .or modifications can be made therein without departing from the spirit of the invention and it .is not desired, therefore, to limit the scope of the ,invention ,exceptas pointedoutin the appendedclaims or as dictated by the prior .art.

I claim:

1. The combination of a plurality of code forming means, means for conditioning said code forming means for operation, switch operated means for actuating said conditioning means and operating selected ones of the code forming means, a control device set to one state by said switch operated means and reset to the opposite state by said conditioning means on actuation thereof, a coincidence detector controlled jointly by said device and said switch operated means, and an alarm actuated under control of said coincidence detector when said device is in said one state and the switch operated means is in inoperated condition.

2. The combination according to claim 1 wherein the switch operated means includes a pair of potential sources of which one is more negative than the other, a series connection extending between the sources but opened on each switch operation, a resistor terminating the said connection at the more negative source, and means connected to said resistor and operable on opening of said connection to set said device to said one state.

3. The combination according to claim 2 wherein said device comprises a flip-flop, and the means for setting the same to said one state comprises a puller tube connected to the flip-flop.

4. The combination of means for producing timing signals, a plurality of coding gates conditioned for operation by the timing signals, an electronic element normally in one state of conduction, keyboard key controlled means for actuating the timing signal producing means, for operating the coding gates selectively, and for changing said electronic element to the opposite state of conduction, a control device having two stable states, means controlled by said electronic element when the latter is in said opposite state to set said control device to one state, means controlled by a timing signal to reset said control device, a coincidence detector controlled by said element and said control device to operate when the former is in its normal state and the latter is in the set state, and an alarm actuated by said coincidence detector on operation thereof.

5. The combination according to claim 4 wherein the control device comprises an electronic flip-flop.

6. The combination according to claim 5 wherein the means for setting the flip-flop include a puller tube and a dilferentiating circuit connected between the latter and said electronic element.

References Cited in the file of this patent UNITED STATES PATENTS 

